`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:35:21 08/23/2012
// Design Name:   fms
// Module Name:   C:/Users/maye/Desktop/alle archivos/lab2/pru_fms.v
// Project Name:  lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: fms
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module pru_fms;

	// Inputs
	reg reset_sync;
	reg sensor_sync;
	reg wr;
	reg prog_sync;
	reg expired;
	reg clk_i;

	// Outputs
	wire wr_reset;
	wire start_timer;
	wire [7:0] busleds;
	wire [1:0] interval;

	// Instantiate the Unit Under Test (UUT)
	fms uut (
		.reset_sync(reset_sync), 
		.sensor_sync(sensor_sync), 
		.wr(wr), 
		.wr_reset(wr_reset), 
		.prog_sync(prog_sync), 
		.interval(interval), 
		.start_timer(start_timer), 
		.expired(expired), 
		.busleds(busleds), 
		.clk_i(clk_i)
	);

	always begin 
		#50 clk_i=~clk_i;
		end 
	initial begin
		// Initialize Inputs
		reset_sync = 0;
		sensor_sync = 0;
		wr = 0;
		prog_sync = 0;
		expired = 1;
		clk_i = 0;

		// Wait 100 ns for global reset to finish
		#1000;
      sensor_sync = 1; 
		#1000;
		wr = 1;
		// Add stimulus here

	end
      
endmodule

